1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor memory device and, more specifically, to a method for manufacturing a semiconductor memory device which is improved in field ion implantation.
2. Description of the Related Art
According to a conventional method for manufacturing a commonly-used nonvolatile semiconductor memory device, a field oxide film is formed on a substrate and separated into element forming regions such as a source region, and word lines and the like are formed on the substrate. This method, however, requires a space for matching, for example, the source region and word lines with each other, which is a hindrance to miniaturization of memory cells.
To resolve this problem, a method for manufacturing a semiconductor memory device is proposed in which a field oxide film is etched using a word line as a mask to expose the surface of a substrate and thus form a source region. Hereinafter, this method is called an SAS (Self Aligned Source) process wherein the source region is self-aligned with the word line. This method is disclosed in Y. Oshima et al., "Process and Device Technologies for 16 Mbit EPROMs with Large-Tilt-Angle Implanted P-pocket Cell," IEDM Technical Digest, Dec. 9, 1990, pp. 95-98.
The SAS process has the advantage of requiring no spaces for matching a source region and a word line with each other and offers easy miniaturizing of memory cells. Since, however, a source line forming region is formed by etching a field oxide film, a channel stopper diffusion layer and a source diffusion layer contact with each other. The channel stopper diffusion layer is formed under the field oxide film. Both the diffusion layers have a high impurity concentration. In particular, since the channel stopper diffusion layer is of the same conductivity type as that of the substrate, if it contacts the source diffusion layer, a withstanding voltage between the source diffusion layer and the substrate is dropped.
The drop in the withstanding voltage is a great drawback to a flash EEPROM in which electrons are extracted from a floating gate by applying a high voltage to the source diffusion layer. The impurity concentration of the channel stopper region has to increase in accordance with the miniaturization of the memory cells. Since, however, a tunnel oxide film of the memory cell cannot be easily scaled, the voltage applied to the source diffusion layer is not decreased too much.
Conventionally, the channel stopper diffusion layer is formed entirely under the field oxide film. Therefore, impurities included in the channel stopper diffusion layer are diffused into a channel region to increase the threshold voltage of a transistor, that is, to induce a so-called "narrow channel effect."